DRAM semiconductor memories are configured as arrays, in which rows correspond to word lines and columns correspond to bit lines. During memory access, a word line is activated in an initial operation, such that memory cells arranged in an activated row are electrically connected to a bit line. The bit line leads to a sense amplifier (SA), which detects and amplifies the cell signal transmitted via the bit line. An amplified signal is written back to the cell or it can be read out externally.
In order to achieve an arrangement of the cell array that is as compact as possible, it is desirable to construct bit lines to be as long as possible. However, this unfortunately leads to a reduction of the signal to be detected by the sense amplifier.
The accompanying FIG. 1 illustrates a known division of a memory cell array in a DRAM into individual blocks 1, 2, 3, and 4. The sense amplifiers are situated in so-called “SA strips” 11, 12, and 13 located between two adjacent cell blocks. In order to save space, a sense amplifier lying in an SA strip, for example 12, between two adjacent cell blocks 2 and 3, is used jointly either for bit line (BL) 5 coming from the left-hand cell block 2 or for bit line 6, coming from right-hand cell block 3. When communicating to sense amp 12, either bit line 5 or bit line 6 is connected to an activated word line WL. For simplification, FIG. 1 shows only a single word line 9 in cell array 3. This arrangement is generally referred to as a “shared SA structure”.
FIG. 2 illustrates further details of such a known shared SA structure, in which a sense amplifier SA is provided jointly for two bit lines 5 and 6 coming from a left-hand and right-hand cell block 2 and 3. It should be noted here that information signals traveling from and to the memory cells are passed in the form of differential signals on complementary bit lines BLT and BLC. Such complementary bit lines are referred to as a bit line pair. For simplification, the illustration of a memory cell attached to the bit line pair shows only a storage capacitor 10 and an associated selection transistor T. Selection transistor T is activated by a word line signal WL via word line 9. Each bit line pair that is allocated to a common sense amplifier is provided with isolation and connection switches S5 and S6, the switching states of which are set by connection control signal ISO left, via a first line 21, and ISO right via a second line 22, respectively.
European Patent No. EP 0 892 409 A2 describes a semiconductor memory (cf. FIG. 10 of the patent, enclosed herein and labeled as FIG. 3), in which four bit line pairs from two adjacent cell blocks can be connected to each sense amplifier (for example SA0, SA1, A2). The description with regard to FIG. 3 from the patent reveals that the bit line pairs that can be connected from a cell block to the respective sense amplifier, as far as the content of the memory cells is concerned, are not independent bit line pairs. Instead, each bit line and each complementary bit line, at the intermediate grounding point of a submatrix, is subdivided into two bit lines toward the right and two bit lines toward the left. Thus, for example, left-hand side bit line pair BL01 and BL01; complementary can be connected to sense amplifier SA0 and right-hand side bit line pair BL0R and BL0R; complementary can likewise be connected to sense amplifier SA0 by means of a line pair ML0, ML0; complementary routed in a connection layer lying above the bit lines. This concept is referred to as an “extended bit line system” in the document. Moreover, 128 sense amplifiers are used for, for example, 256 bit line pairs of a submatrix in each sense amplifier block.